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1 document # sram110 rev a revised october 2005 p4c116/p4c116l ultra high speed 2k x 8 static cmos rams description the p4c116/p4c116l are 16,384-bit ultra high-speed static rams organized as 2k x 8. the cmos memories require no clocks or refreshing and have equal access and cycle times. inputs are fully ttl-compatible. the rams operate from a single 5v10% tolerance power supply. current drain is typically 10 a from a 2.0v supply. access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. cmos is used to reduce power consumption. the p4c116 is available in 24-pin 300 mil dip, soj and soic packages, a solder seal flatpack and 4 different lcc packages (24, 28, 32, and 40 pin). functional block diagram pin configurations features full cmos, 6t cell high speed (equal access and cycle times) ? 10/12/15/20/25/35 ns (commercial) ? 15/20/25/35 ns (military) low power operation output enable control function single 5v10% power supply common data i/o fully ttl compatible inputs and outputs produced with pace ii technology tm standard pinout (jedec approved) ? 24-pin 300 mil dip, soic, soj ? 24-pin solder seal flat pack ? 24-pin rectangular lcc (300 x 400 mils) ? 28-pin square lcc (450 x 450 mils) ? 32-pin rectangular lcc (450 x 550 mils) ? 40-pin square lcc (480 x 480 mils) lcc configurations at end of datasheet dip (p4, c4), soj (j4), soic (s4) solder seal flat pack (fs-1) similar
p4c116/p4c116l page 2 of 14 document # sram110 rev a maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma symbol parameter conditions typ. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf grade (2) ambient temp gnd vcc commercial 0c to 70c 0v 5.0v 10% military -55c to +125c 0v 5.0v 10% recommended operating conditions capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) dc electrical characteristics over recommended operating temperature and supply voltage (2) i sb standby power supply current (ttl input levels) ce v ih, mil. v cc = max, ind./com?l. f = max., outputs open ___ ___ 30 20 ___ ___ ___ ___ 15 10 20 n/a 1 n/a ma ma ___ ___ ce v hc , mil. v cc = max, ind./com?l. f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 symbol v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current test conditions v cc = min., i in = ?18 ma i ol = +8 ma, v cc = min. i oh = ?4 ma, v cc = min. v cc = max. mil. v in = gnd to v cc com?l. v cc = max., ce = v ih , mil. v out = gnd to v cc com?l. p4c116 min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?10 ?5 ?10 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +10 +5 +10 +5 p4c116l min max 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?5 n/a ?5 n/a v cc +0.5 0.8 v cc +0.5 0.2 0.4 ?1.2 +5 n/a +5 n/a unit v v v v v v v a a n/a = not applicable
p4c116/p4c116l page 3 of 14 document # sram110 rev a ac electrical characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) sym. t rc t aa t ac t oh t lz t hz t oe t olz t ohz t pu t pd parameter output enable low to data valid chip enable to power up time chip disable to power down read cycle time address access time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z output enable low to low z output enable high to high z ?10 min max ?12 min max ?15 min max ?20 min max ?25 min max ?35 min max unit 15 15 15 2 2 7 10 0 8 0 15 20 2 2 0 0 20 20 8 10 9 20 25 2 3 0 0 25 25 10 15 12 20 35 2 3 0 0 35 35 15 20 15 25 ns ns ns ns ns ns ns ns ns ns ns 10 2 2 0 0 10 10 5 10 12 2 2 0 0 12 12 6 12 *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . i cc symbol parameter temperature range dynamic operating current* commercial military ?10 n/a ?12 ?20 ?25 ?35 unit ma ma power dissipation characteristics vs. speed n/a 170 160 155 150 180 170 160 155 150 140 ?15 67 8 6 data retention characteristics (p4c116l military temperature only) symbol v dr i ccdr t cdr t r ? parameter v cc for data retention data retention current chip deselect to data retention time operation recovery time test conditons ce v cc ?0.2v, v in v cc ?0.2v or v in 0.2v min 2.0 0 t rc typ.* v cc = 2.0v 3.0v max v cc = 2.0v 3.0v unit 10 15 600 900 v a ns ns *t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. data retention waveform
p4c116/p4c116l page 4 of 14 document # sram110 rev a timing waveform of read cycle no. 2 (address controlled) (5,6) timing waveform of read cycle no. 3 (ce controlled) (5,7) notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the first transitioning address. timing waveform of read cycle no. 1 ( oe oe oe oe oe controlled) (5)
p4c116/p4c116l page 5 of 14 document # sram110 rev a ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) timing waveform of write cycle no. 1 ( we we we we we controlled) (10,11) notes: 10. ce and we must be low for write cycle. 11. oe is low for this write cycle to show t wz and t ow . 12. if ce goes high simultaneously with we high, the output remains in a high impedance state 13. write cycle time is measured from the last valid address to the first transitioning address. t wc sym. t cw t aw t as t wp t ah t dw t dh t wz t ow parameter write cycle time chip enable time to end of write address valid to end of write address set-up time write pulse width address hold time data valid to end of write data hold time write enable to output in high z output active from end of write ?10 ?12 ?15 ?20 ?25 ?35 unit min max min max min max min max min max min max 15 12 12 0 12 0 10 0 0 8 20 15 15 0 15 0 12 0 0 10 25 18 18 0 18 0 15 0 0 15 35 25 25 0 20 0 20 0 0 15 ns ns ns ns ns ns ns ns ns ns timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (10) 10 8 8 0 8 0 7 0 0 6 12 10 10 0 10 0 8 0 0 7
p4c116/p4c116l page 6 of 14 document # sram110 rev a mode ce ce ce ce ce oe oe oe oe oe we we we we we i/o power standby h x x high z standby d out disabled l h h high z active read l l h d out active write l x l high z active input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 ac test conditions truth table figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: because of the ultra-high speed of the p4c116/l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance).
p4c116/p4c116l page 7 of 14 document # sram110 rev a 24-pin lcc (l8) 28-pin lcc (l5-1) lcc pin configurations 32-pin lcc (l6) 40-pin lcc (l10)
p4c116/p4c116l page 8 of 14 document # sram110 rev a ordering information * military temperature range with mil-std-883, class b processing. n/a = not available selection guide the p4c116 is available in the following temperature, speed and package options. 10 12 15 20 25 35 plastic dip -10pc -12pc -15pc -20pc -25pc -35pc plastic soj -10jc -12jc -15jc -20jc -25jc -35jc plastic soic -10sc -12sc -15sc -20sc -25sc -35sc 24-pin rect. lcc n/a n/a -15lm -20lm -25lm -35lm 28-pin sq. lcc n/a n/a -15l28m -20l28m -25l28m -35l28m 32-pin rect. lcc n/a n/a -15l32m -20l32m -25l32m -35l32m 40-pin sq. lcc n/a n/a -15l40m -20l40m -25l40m -35l40m side brazed dip n/a n/a -15cm -20cm -25cm -35cm cerpack n/a n/a -15fsm -20fsm -25fsm -35fsm 24-pin rect. lcc n/a n/a -15lmb -20lmb -25lmb -35lmb 28-pin sq. lcc n/a n/a -15l28mb -20l28mb -25l28mb -35l28mb 32-pin rect. lcc n/a n/a -15l32mb -20l32mb -25l32mb -35l32mb 40-pin sq. lcc n/a n/a -15l40mb -20l40mb -25l40mb -35l40mb side brazed dip n/a n/a -15cmb -20cmb -25cmb -35cmb cerpack n/a n/a -15fsmb -20fsmb -25fsmb -35fsmb speed (ns) commercial military processed* military temperature temperature range package
p4c116/p4c116l page 9 of 14 document # sram110 rev a side brazed dual in-line package pkg # # pins symbol min max a - 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.280 e 0.220 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - 0.100 bsc c4 24 (300 mil) 0.300 bsc pkg # # pins symbol min max a 0.045 0.115 b 0.015 0.022 b1 0.015 0.019 c 0.004 0.009 c1 0.004 0.006 d - 0.640 e 0.350 0.420 e1 - 0.450 e2 0.180 - e3 0.030 - e k 0.008 0.015 l 0.250 0.370 q 0.026 0.045 s1 0.000 - m - 0.0015 n 0.050 bsc 24 fs-1 24 solder seal flatpack
p4c116/p4c116l page 10 of 14 document # sram110 rev a soj small outline ic package pkg # # pins symbol min max a 0.128 0.148 a1 0.082 - b 0.016 0.020 c 0.007 0.010 d 0.620 0.630 e e e1 0.292 0.300 e2 q0.025- j4 24 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc square leadless chip carrier pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d/e 0.442 0.460 d1/e1 d2/e2 d3/e3 - 0.460 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.050 bsc 7 l5-1 28 0.300 bsc 0.150 bsc 7 0.040 ref 0.020 ref
p4c116/p4c116l page 11 of 14 document # sram110 rev a rectangular leadless chip carrier pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.442 0.458 d1 d2 d3 - 0.458 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne l6 32 0.300 bsc 0.150 bsc 0.020 ref 7 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref pkg # # pins symbol min max a 0.064 0.076 a1 0.054 0.066 b1 0.022 0.028 d 0.292 0.308 d1 d2 d3 - 0.308 e 0.392 0.408 e1 e2 e3 - 0.408 e h j l 0.040 0.050 l1 0.040 0.050 l2 0.077 0.093 nd ne l8 24 0.200 bsc 0.100 bsc 0.015 ref 5 7 0.300 bsc 0.150 bsc 0.050 bsc 0.025 ref rectangular leadless chip carrier
p4c116/p4c116l page 12 of 14 document # sram110 rev a pkg # # pins symbol min max a 0.060 0.080 a1 0.050 0.075 b1 0.015 0.025 d/e 0.475 0.492 d1/e1 d2/e2 d3/e3 - 0.492 e h j l 0.030 0.050 l1 0.030 0.050 l2 0.080 0.090 nd/ne 0.040 bsc l10 40 0.360 bsc 0.180 bsc 10 r = .0075 0.026 ref pkg # # pins symbol min max a-0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 1.230 1.280 e1 0.240 0.280 e 0.300 0.325 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p4 24 (300 mil) square leadless chip carrier plastic dual in-line package
p4c116/p4c116l page 13 of 14 document # sram110 rev a pkg # # pins symbol min max a 0.093 0.104 a1 0.004 0.012 b2 0.013 0.020 c 0.009 0.012 d 0.598 0.614 e e 0.291 0.299 h 0.394 0.419 h 0.010 0.029 l 0.016 0.050 0 8 s4 24 (300 mil) 0.050 bsc soic/sop small outline ic package
p4c116/p4c116l page 14 of 14 document # sram110 rev a revisions document number : sram110 document title : p4c116 / p4c116l ultra high speed 2k x 8 static cmos rams rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid

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